====== Xilinx Virtex-5 FXT Evaluation Kit ======
 * [[http://www.em.avnet.com/evk/home/0,4534,CID%253D46471%2526CCD%253DUSA%2526SID%253D32214%2526DID%253DDF2%2526LID%253D32232%2526BID%253DDF2%2526CTP%253DEVK,00.html?SUL=virtex5fxt-evl | Eval board description on Avnet page ]]

The Xilinx Virtex-5 FXT Evaluation Kit provides the necessary features for exploring PowerPC 440 based system architectures using the Xilinx Virtex-5 FXT FPGA family. This low cost evaluation platform is ideal for both software and FPGA designers needing an easy to use, entry level system for code development and debug, processor systems prototyping, and general FXT evaluation.

The Virtex-5 FXT system board uses the Xilinx Virtex-5 FX30T-1 FPGA in the FFG665 package. With over 32,000 logic cells, 64 DSP-48 slices, embedded PowerPC 440 core, and built-in 10/100/1000 Ethernet MAC, the FX30T FPGA provides the essential building blocks for system integration needs. The system board includes 64 MB of DDR2 SDRAM, 16 MB of parallel Flash memory, a 10/100/1000 Ethernet PHY device, an RS-232 and USB-to-UART serial port, and an assortment of LEDs and switches. FPGA configuration is accomplished through a JTAG port connector, parallel Flash BPI mode, or through the System ACE interface with an optional System ACE module. PowerPC development is aided through a dedicated debug and TRACE port. An on-board 100 MHz clock oscillator provides the system clock or alternative clocking can be added through the user oscillator socket or an external LVDS compatible clock input port. The half EXP expansion slot supports up to 84 user I/O in both single-ended and differential formats.

=== Key Features=== 

    * Xilinx XC5VFX30T-1FFG665 Virtex-5 FPGA
    * Eight LEDs
    * DIP switches
    * Four push-button switches
    * On-board 100 MHz LVTTL oscillator
    * User clock inputs via differential SMA connectors
    * EXP half expansion slot
    * System ACE™ module header
    * 64 MB DDR2 SDRAM
    * 16 MB Flash
    * RS-232 and USB-UART serial ports
    * 10/100/1000 Ethernet PHY
    * System ACE option
    * Xilinx JTAG interface
    * BPI Configuration
    * Trace and debugger port for PPC 

=== Target Applications=== 

    * PowerPC™ 440 software development
    * General FPGA prototyping
    * Communications systems
    * Image processing

=== Foto=== 
 {{  :hw:fpga:virtex5fxt:xlx-drc-virtex5fxt-evl.jpg  }}
    * {{:hw:fpga:virtex5fxt:v5fxt_block_diagram_021108.pdf|Xilinx Virtex-5 FXT Evaluation Kit - Block Diagram}}
    * {{:hw:fpga:virtex5fxt:xlx_v5fxt_evl-pb052208f.pdf|Xilinx Virtex-5 FXT Evaluation Kit - Product Brief}}
    * {{:hw:fpga:virtex5fxt:exp_specification_v1_4.pdf|EXP Expansion Connector Specification}}

==== App Notes/Ref Designs ====

   * {{ :hw:fpga:virtex5fxt:Virtex5-FX30T_PPC_125_Net_Perf_LL_TEMAC_SDMA_MPMC.zip |FXT Evaluation Network Performance Example Design}}
   * {{ :hw:fpga:virtex5fxt:fxt_evaluation_temac_lwip_web_server_edk10_1_02.zip |FXT Evaluation TEMAC lwIP Web Server Example Design}}
   * {{ :hw:fpga:virtex5fxt:fxt_evaluation_systemace_module_edk10_1_02.zip |FXT Evaluation SystemACE Module Example Design}}
   * {{ :hw:fpga:virtex5fxt:fxt_evaluation_ppc_xmk_edk10_1_02.zip |FXT Evaluation Xilinx Micro Kernel (XMK) Example Design}}
   * {{ :hw:fpga:virtex5fxt:fxt_evaluation_multi_boot_edk10_1_02.zip |FXT Evaluation Multi-Boot Example Design}}
   * {{ :hw:fpga:virtex5fxt:fxt_evaluation_git_linux_edk10_1_3.zip |FXT Evaluation git Linux Example Design}}
   * {{ :hw:fpga:virtex5fxt:fxt_evaluation_executing_from_flash_edk10_1_02.zip |FXT Evaluation Executing From Flash Example Design}}
   * {{ :hw:fpga:virtex5fxt:fxt_evaluation_bootloader_edk10_1_02.zip |FXT Evaluation Boot Loader Example Design}}
   * {{ :hw:fpga:virtex5fxt:fxt_evaluation_bc_linux_edk10_1_3.zip |FXT Evaluation BlueCat Linux Example Design}}

==== BOM ====
   * {{:hw:fpga:virtex5fxt:xlx_v5_fxt_evl-bom.pdf | Xilinx Vritex-5 FXT Evaluation Kit - BOM}}

==== Other ====
   * {{:hw:fpga:virtex5fxt:v5fx30t_eval_ucf.zip |V5FX30T .ucf}}
   * {{:hw:fpga:virtex5fxt:CP2102_USB_Drivers.zip |CP2102 USB Drivers.zip}}
==== Schematics ====
   * {{:hw:fpga:virtex5fxt:xlx_v5fxt_evl-sch-revb.pdf.pdf |Xilinx Virtex-5 FXT Evaluation Kit - Schematics}}
==== Test Files ====
   * {{:hw:fpga:virtex5fxt:v5fx30t_test_files.zip |V5FX30T Functional Tests (.bit)}}

==== User Guide ====
   * {{:hw:fpga:virtex5fxt:xlx_v5fxt_evl-ug-rev1.pdf |Xilinx Virtex-5 FXT Evaluation Kit - User Guide}}
==== XBD ====
   * {{:hw:fpga:virtex5fxt:avnet_edk10_1_xbd_files_090212-13.zip |XBD Files (EDK 10.1 or later)}}


==== Other Xilinx  app notes ====
   * {{:hw:fpga:virtex5fxt:ug198.pdf| Virtex-5 FPGA RocketIO GTX Transceiver User Guide (ug198) }}
   * {{:hw:fpga:virtex5fxt:p105-107_57-bellinix.pdf| Selecting a High-Speed POL Converter for FPGAs }}
   * {{:hw:fpga:virtex5fxt:serialio-book.pdf|High-Speed Serial I/O Made Simple}}

==== Prom INFO ====
   * 28F128P30
   * 16 M 
   * 16 bit