EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# NAME DIR [LSB:MSB] SIG ATTRIBUTES fpga_0_RS232_sin_pin I 1 fpga_0_RS232_sin fpga_0_RS232_sout_pin O 1 fpga_0_RS232_sout fpga_0_LEDs_8Bit_GPIO_d_out_pin O 0:7 fpga_0_LEDs_8Bit_GPIO_d_out fpga_0_DIP_Switches_8Bit_GPIO_in_pin I 0:7 fpga_0_DIP_Switches_8Bit_GPIO_in fpga_0_Push_Buttons_3Bit_GPIO_in_pin I 0:2 fpga_0_Push_Buttons_3Bit_GPIO_in fpga_0_FLASH_8Mx16_Mem_DQ_pin IO 0:15 fpga_0_FLASH_8Mx16_Mem_DQ fpga_0_FLASH_8Mx16_Mem_A_pin O 7:31 fpga_0_FLASH_8Mx16_Mem_A fpga_0_FLASH_8Mx16_Mem_WEN_pin O 1 fpga_0_FLASH_8Mx16_Mem_WEN fpga_0_FLASH_8Mx16_Mem_OEN_pin O 0:0 fpga_0_FLASH_8Mx16_Mem_OEN fpga_0_FLASH_8Mx16_Mem_CEN_pin O 0:0 fpga_0_FLASH_8Mx16_Mem_CEN fpga_0_FLASH_8Mx16_rpn_dummy_pin O 1 net_vcc fpga_0_FLASH_8Mx16_byte_dummy_pin O 1 net_vcc fpga_0_FLASH_8Mx16_adv_dummy_pin O 1 net_gnd fpga_0_FLASH_8Mx16_clk_dummy_pin O 1 net_vcc fpga_0_FLASH_8Mx16_wait_dummy_pin O 1 net_gnd fpga_0_DDR2_SDRAM_16Mx32_DDR2_ODT_pin O 0:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_ODT fpga_0_DDR2_SDRAM_16Mx32_DDR2_A_pin O 12:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_A fpga_0_DDR2_SDRAM_16Mx32_DDR2_BA_pin O 1:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_BA fpga_0_DDR2_SDRAM_16Mx32_DDR2_CAS_N_pin O 1 fpga_0_DDR2_SDRAM_16Mx32_DDR2_CAS_N fpga_0_DDR2_SDRAM_16Mx32_DDR2_CKE_pin O 1 fpga_0_DDR2_SDRAM_16Mx32_DDR2_CKE fpga_0_DDR2_SDRAM_16Mx32_DDR2_CS_N_pin O 1 fpga_0_DDR2_SDRAM_16Mx32_DDR2_CS_N fpga_0_DDR2_SDRAM_16Mx32_DDR2_RAS_N_pin O 1 fpga_0_DDR2_SDRAM_16Mx32_DDR2_RAS_N				# NAME DIR [LSB:MSB] SIG ATTRIBUTES fpga_0_DDR2_SDRAM_16Mx32_DDR2_WE_N_pin O 1 fpga_0_DDR2_SDRAM_16Mx32_DDR2_WE_N fpga_0_DDR2_SDRAM_16Mx32_DDR2_DM_pin O 3:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_DM fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS IO 3:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_N IO 3:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_N fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQ IO 31:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQ fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_pin O 1:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_N_pin O 1:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_N fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin O 1 fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin O 7:0 fpga_0_Hard_Ethernet_MAC_GMII_TXD_0 fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin O 1 fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0 fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin O 1 fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0 fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin O 1 fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0 fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin I 1 fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0 fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin I 1 fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0 fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin I 1 fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0 fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin I 7:0 fpga_0_Hard_Ethernet_MAC_GMII_RXD_0 fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin I 1 fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0 fpga_0_Hard_Ethernet_MAC_MDC_0_pin O 1 fpga_0_Hard_Ethernet_MAC_MDC_0 fpga_0_Hard_Ethernet_MAC_MDIO_0_pin IO 1 fpga_0_Hard_Ethernet_MAC_MDIO_0 fpga_0_Hard_Ethernet_MAC_PHY_MII_INT_pin O 1 net_vcc sys_clk_pin I 1 dcm_clk_s  CLK  sys_rst_pin I 1 sys_rst_s  RESET