EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# NAME DIR [LSB:MSB] SIG ATTRIBUTES 0A fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQ IO 31:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQ 1A fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS IO 3:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS 2A fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_N IO 3:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_N 3A fpga_0_DDR2_SDRAM_16Mx32_DDR2_A_pin O 12:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_A 4A fpga_0_DDR2_SDRAM_16Mx32_DDR2_BA_pin O 1:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_BA 5A fpga_0_DDR2_SDRAM_16Mx32_DDR2_CAS_N_pin O 1 fpga_0_DDR2_SDRAM_16Mx32_DDR2_CAS_N 6A fpga_0_DDR2_SDRAM_16Mx32_DDR2_CKE_pin O 1 fpga_0_DDR2_SDRAM_16Mx32_DDR2_CKE 7A fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_N_pin O 1:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_N 8A fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_pin O 1:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK 9A fpga_0_DDR2_SDRAM_16Mx32_DDR2_CS_N_pin O 1 fpga_0_DDR2_SDRAM_16Mx32_DDR2_CS_N				# NAME DIR [LSB:MSB] SIG ATTRIBUTES 10A fpga_0_DDR2_SDRAM_16Mx32_DDR2_DM_pin O 3:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_DM 11A fpga_0_DDR2_SDRAM_16Mx32_DDR2_ODT_pin O 0:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_ODT 12A fpga_0_DDR2_SDRAM_16Mx32_DDR2_RAS_N_pin O 1 fpga_0_DDR2_SDRAM_16Mx32_DDR2_RAS_N 13A fpga_0_DDR2_SDRAM_16Mx32_DDR2_WE_N_pin O 1 fpga_0_DDR2_SDRAM_16Mx32_DDR2_WE_N 14B fpga_0_LEDs_8Bit_GPIO_d_out_pin O 0:7 fpga_0_LEDs_8Bit_GPIO_d_out 15C fpga_0_RS232_RX_pin I 1 fpga_0_RS232_RX 16C fpga_0_RS232_TX_pin O 1 fpga_0_RS232_TX 17D sys_clk_pin I 1 dcm_clk_s  CLK  18E sys_rst_pin I 1 sys_rst_s  RESET