EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# NAME DIR [LSB:MSB] SIG ATTRIBUTES 0GLB fpga_0_Hard_Ethernet_MAC_PHY_MII_INT_pin O 1 net_vcc 1A fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQ IO 31:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQ 2A fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS IO 3:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS 3A fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_N IO 3:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_DQS_N 4A fpga_0_DDR2_SDRAM_16Mx32_DDR2_A_pin O 12:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_A 5A fpga_0_DDR2_SDRAM_16Mx32_DDR2_BA_pin O 1:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_BA 6A fpga_0_DDR2_SDRAM_16Mx32_DDR2_CAS_N_pin O 1 fpga_0_DDR2_SDRAM_16Mx32_DDR2_CAS_N 7A fpga_0_DDR2_SDRAM_16Mx32_DDR2_CKE_pin O 1 fpga_0_DDR2_SDRAM_16Mx32_DDR2_CKE 8A fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_N_pin O 1:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_N 9A fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK_pin O 1:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_CK 10A fpga_0_DDR2_SDRAM_16Mx32_DDR2_CS_N_pin O 1 fpga_0_DDR2_SDRAM_16Mx32_DDR2_CS_N 11A fpga_0_DDR2_SDRAM_16Mx32_DDR2_DM_pin O 3:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_DM 12A fpga_0_DDR2_SDRAM_16Mx32_DDR2_ODT_pin O 0:0 fpga_0_DDR2_SDRAM_16Mx32_DDR2_ODT 13A fpga_0_DDR2_SDRAM_16Mx32_DDR2_RAS_N_pin O 1 fpga_0_DDR2_SDRAM_16Mx32_DDR2_RAS_N 14A fpga_0_DDR2_SDRAM_16Mx32_DDR2_WE_N_pin O 1 fpga_0_DDR2_SDRAM_16Mx32_DDR2_WE_N 15B fpga_0_DIP_Switches_8Bit_GPIO_in_pin I 0:7 fpga_0_DIP_Switches_8Bit_GPIO_in 16C fpga_0_Hard_Ethernet_MAC_GMII_RXD_0_pin I 7:0 fpga_0_Hard_Ethernet_MAC_GMII_RXD_0				# NAME DIR [LSB:MSB] SIG ATTRIBUTES 17C fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0_pin I 1 fpga_0_Hard_Ethernet_MAC_GMII_RX_CLK_0 18C fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0_pin I 1 fpga_0_Hard_Ethernet_MAC_GMII_RX_DV_0 19C fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0_pin I 1 fpga_0_Hard_Ethernet_MAC_GMII_RX_ER_0 20C fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0_pin I 1 fpga_0_Hard_Ethernet_MAC_MII_TX_CLK_0 21C gbe_mclk I 1 gtx_clk  CLK  22C fpga_0_Hard_Ethernet_MAC_MDIO_0_pin IO 1 fpga_0_Hard_Ethernet_MAC_MDIO_0 23C fpga_0_Hard_Ethernet_MAC_GMII_TXD_0_pin O 7:0 fpga_0_Hard_Ethernet_MAC_GMII_TXD_0 24C fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0_pin O 1 fpga_0_Hard_Ethernet_MAC_GMII_TX_CLK_0 25C fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0_pin O 1 fpga_0_Hard_Ethernet_MAC_GMII_TX_EN_0 26C fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0_pin O 1 fpga_0_Hard_Ethernet_MAC_GMII_TX_ER_0 27C fpga_0_Hard_Ethernet_MAC_MDC_0_pin O 1 fpga_0_Hard_Ethernet_MAC_MDC_0 28C fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n_pin O 1 fpga_0_Hard_Ethernet_MAC_TemacPhy_RST_n 29D fpga_0_LEDs_8Bit_GPIO_d_out_pin O 0:7 fpga_0_LEDs_8Bit_GPIO_d_out 30E fpga_0_RS232_RX_pin I 1 fpga_0_RS232_RX 31E fpga_0_RS232_TX_pin O 1 fpga_0_RS232_TX 32F sys_clk_pin I 1 dcm_clk_s  CLK  33G sys_rst_pin I 1 sys_rst_s  RESET